Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

被引：6

作者：

Kim, Y. ^{[1
]}

Seo, S-C ^{[2
]}

Consiglio, S. ^{[3
]}

Jamison, P. ^{[2
]}

Higuchi, H. ^{[3
]}

Rasch, M. ^{[1
]}

Wu, E. Y. ^{[2
]}

Kong, D. ^{[2
]}

Saraf, I ^{[2
]}

Catano, C. ^{[3
]}

Muralidhar, R. ^{[1
]}

Nguyen, S. ^{[2
]}

DeVries, S. ^{[2
]}

Van der Straten, O. ^{[2
]}

Sankarapandian, M. ^{[2
]}

Pujari, R. N. ^{[2
]}

Gasasira, A. ^{[2
]}

Mcdermott, S. M. ^{[2
]}

Miyazoe, H. ^{[1
]}

Koty, D. ^{[3
]}

Yang, Q. ^{[3
]}

Yan, H. ^{[1
]}

Clark, R. ^{[3
]}

Tapily, K. ^{[3
]}

Engelmann, S. ^{[1
]}

Robison, R. R. ^{[2
]}

Wajda, C. ^{[3
]}

Mosden, A. ^{[3
]}

Tsunomura, T. ^{[4
]}

Soave, R. ^{[5
]}

Saulnier, N. ^{[2
]}

Haensch, W. ^{[1
]}

Leusink, G. ^{[3
]}

Biolsi, P. ^{[3
]}

Narayanan, V ^{[1
]}

Ando, T. ^{[1
]}

机构：

[1] IBM Res, Yorktown Hts, NY 10598 USA

[2] IBM Res, Albany, NY 12203 USA

[3] TEL Technol Ctr America LLC, Albany, NY 12203 USA

[4] Tokyo Electron Ltd, Tokyo 1076325, Japan

[5] Tokyo Electron Amer Inc, Austin, TX 78741 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2021年 / 42卷 / 05期

关键词：

Resistance; Reservoirs; Plasmas; Switches; Electrodes; Hafnium oxide; Standards; Analog compute; cross-bar array; plasma process; ReRAM;

D O I：

10.1109/LED.2021.3066181

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a novel process for building a Resistive RAM (ReRAM) stack which reduces the forming voltage (V-form) and increases the switching resistance, both characteristics that are important ingredients for the use of ReRAM in scalable analog compute for AI. Utilizing this process, we explore analog switching characteristics above 100k and demonstrate 4-bit programming at Rmax = 1M. Utilizing the same writing characteristics, CIFAR-10 inference simulation shows 90% accuracy, comparable to the full precision model accuracy.

引用

页码：759 / 762

页数：4

共 28 条

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Miyazoe, H.
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