Power Consumption Contrasting Model for Different Logarithmic Active Pixel Sensor Topologies

The literature presents many different active pixel sensor (APS) topologies operating in the high dynamic range logarithmic mode, as well as, different techniques to improve image quality by attenuating fixed-pattern noise (FPN). Together with the proposed solution, the advantages and disadvantages of each new solution are usually presented in their published reports. However, it is hard to find different solutions developed for the very same CMOS technology, and there is no standard model to effectively contrast their effectiveness according to parameters such as power consumption. This work analyses the power consumption of different logarithmic mode CMOS APSs topologies employing different FPN attenuation techniques. The purpose of such a study is the establishment of a way to contrast different solutions designed in the same CMOS technology, so that one can easily make a decision on what solution to choose based on different parameters, including power consumption.