Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers

被引:2
|
作者
Woo, DS [1 ]
Kim, KW
Lim, SK
Ko', J
机构
[1] Kyungpook Natl Univ, Sch Elect Engn & Comp Sci, Taegu 702701, South Korea
[2] Elect & Telecommun Res Inst, Taejon 305606, South Korea
关键词
clock recovery (CR); 40; Gb/s; phase-locked loop (PLL); clock and data recovery (CDR); jitter;
D O I
10.1002/mop.21335
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A low-cost, compact, high-performance clock-recovery (CR) module using a new phase-locked loop (PLL) for 40-Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency 7 detector in the PLL helps to reduce the current consumption and also extended the frequency-capture range. The implemented PLL clock-recovery module demonstrates advantages over the conventional open-loop type clock-recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error-free operation during a 30-min BER test with a time-division-multiplexing (TDM) 40-Gb/s transmission system. (C) 2005 Wiley Periodicals, Inc.
引用
收藏
页码:312 / 315
页数:4
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