A novel Redundant Binary Signed-Digit (RBSD) Booth's Encoding

Signed Digit Number representation has been used to form fast multipliers due to the capability of carry-free addition and a more regular layout. Booth's encoding and its variations are also employed to design fast multipliers by reducing the number of partial products in the multiplication. However Booth's encoding is not efficient for higher than Radix-4 because of the difficulty in generating the necessary hard multiples such as 3 x Multiplicand and the time delay caused by the decoding circuits. To date, the literature reports the use of the Modified Booth's Encoding (MBE) and the Redundant Binary Signed-Digit (RBSD) adders together in the multiplier designs. However, they have been used as separate units: the MBE unit generates the intermediate partial products (PP) in Standard Binary (SB) form and the second unit converts and reduces these PPs into the RBSD partial products to be accumulated by RBSD adders. This paper presents a novel Redundant Binary Signed-Digit Booth's Encoding (RBBE) for a multiplier, which directly generates the RBSD partial products and allows the use of Booth's encoding for Radix-4 and Radix-8 without the need to generate any hard multiples. As for RBBE with higher than Radix-8, the number of hard multiples is significantly reduced. Moreover, negation in RBSD requires only wire crossing of two bits of each digit and does not need any carry-propagate operation or sign-extension. Therefore, the generation of negative multiples or the multiplication of 2's complement numbers in RBSD form can be done without additional hardware. This leads to a faster and smaller size multiplier. RBSD adder tree is used to accumulate these RBSD partial products and the result will be in RBSD form. Although the carry-propagate addition is necessary for the conversion from RBSD to SB, this is not a disadvantage over a SB multiplier because the accumulation of SB partial products also requires the same carry-propagate addition to get the final result from the intermediate Sum and Carry at the last stage.