Enhanced Reduced Code Linearity Test Technique for Multi-bit/Stage Pipeline ADCs

被引：0

作者：

Laraba, Asma ^{[1
]}

Stratigopoulos, Haralampos-G ^{[1
]}

Mir, Salvador ^{[1
]}

Naudet, Herve ^{[2
]}

Forel, Christophe ^{[2
]}

机构：

[1] CNRS Grenoble INP UJF, TIMA Lab, 46 Av Felix Viallet, F-38031 Grenoble, France

[2] STMicroelect, F-38000 Grenoble, France

来源：

2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2012年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

引用

页数：6

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