A speculative multithreading with selective multi-path execution

被引：0

作者：

Ootsu, K ^{[1
]}

Yoshinari, W ^{[1
]}

Furukawa, F ^{[1
]}

Yoshinaga, T ^{[1
]}

Baba, T ^{[1
]}

机构：

[1] Utsunomiya Univ, Dept Informat Sci, Utsunomiya, Tochigi 3210903, Japan

来源：

INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recent microprocessors' performance has been improved by their high-speed clock frequency and by their exploiting instruction-level parallelism (ILP). Physical limitations of clock speed and semantical limitations of control dependencies impede the improvement of performance. To overcome this difficulty, it is indispensable to make use of the thread-level parallelism. This paper proposes a speculative thread execution model that aims at a speed-up of sequential program execution by selective multi-path thread execution.

引用

页码：46 / 52

页数：7

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