Electrical characteristics of a reduced-gate structure polycrystalline silicon thin film transistor using field-aided lateral crystallization

In order to reduce the leakage current in n-channel polycrystalline silicon thin film transistors processed by field-aided lateral crystallization, we applied a reduced gate structure that enables an offset region between the channel and source-drain. The structure in this study was much simpler than those of other methods in the sense that it could accomplish both offset-gate and Ni-offset effects simultaneously without employing any additional masks or processes. The leakage current decreased as the offset region length Delta L per side increased. When Delta L = 2 mu m, which corresponded to 10 percent of the total channel length of L = 20 mu m, the off-state leakage current decreased to 3.2 pA/mu m at V-D = 0.1 V and V-G = -10 V, which is more than two orders of magnitude lower than that in the conventional structure. In addition to a reduction in leakage current, other device parameters did not change significantly.