A Built-in Defective Level Monitor of Resistive Open Defects in 3D ICs with Logic Gates

被引：0
|
作者：
Hashizume, Masaki [1 ]
Odoriba, Akihiro [1 ]
Yotsuyanagi, Hiroyuki [1 ]
Lu, Shyue-Kung [2 ]
机构：
[1] Univ Tokushima, Inst Sci & Technol, Tokushima 7708506, Japan
[2] Natl Taiwan Univ Sci & Technol, Coll Elect Engn & Comp Sci, Taipei 106, Taiwan
来源：
2016 IEEE CPMT SYMPOSIUM JAPAN (ICSJ) | 2016年
关键词：
defect level monitoring; electrical interconnect test; 3D IC; open defect;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Resistive open defects in 3D ICs may change into hard open ones. In this paper, a built-in test circuit is proposed to monitor the changing process of the resistive open defects occurring at interconnects between dies embedding an IEEE 1149.1 test circuit. Feasibility of the process monitoring is examined experimentally in a PCB circuit made of ICs embedding the test circuit. It is shown that the changing process of a resistive open defect can be monitored at a test speed of 500 kHz.
引用
收藏
页码：99 / 102
页数：4
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