Hardware implementations of cryptographic systems are becoming more and more popular, due to new market needs and to reduced costs. However, the security of a system may be seriously compromised by implementation attacks, such as side channel analysis or fault analysis. Thus, a large number of solutions has been proposed to counteract these threats. In this paper, we present an approach to countermeasure against natural or malicious fault injections into a symmetric block cipher PP-2. In PP-2 encrypting a data block consists of repeating a number of identical round. Each round consists of a series of internal transformations and uses a round key derived from the secret key. Decryption is the inverse process of encryption and has a similar structure. Concurrent Error Detection proposed in this paper is based on the inverse relationship that exist between encryption and decryption at the round level and developed architecture that explore relation between area overhead, performance penalty and error detection latency.
