A 20.7 mW Continuous-time ΔΣ Modulator with 15 MHz Bandwidth and 70 dB Dynamic Range

被引：20

作者：

Reddy, Karthikeyan ^{[1
]}

Pavan, Shanthi ^{[1
]}

机构：

[1] Indian Inst Technol, Madras 600036, Tamil Nadu, India

来源：

ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2008年

关键词：

ADC;

D O I：

10.1109/ESSCIRC.2008.4681829

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a CT-Delta Sigma modulator operating at a sampling rate of 300 Msps in a 0.18 mu m CMOS process. A low power four bit flash ADC and a complementary current-steering DAC are used to reduce power and noise. The opamps used in the active-RC loop filter are deliberately made slow to further reduce current consumption and the resulting loop delay is compensated. The modulator achieves a peak SNR of 67.2dB in a 15 MHz bandwidth (OSR=10) while dissipating only 20.7 mW from a 1.8 V supply.

引用

页码：210 / 213

页数：4

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