Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm

被引：0
|
作者：
Kincses, Z. [1 ]
Voeroeshazi, Zs [2 ]
Nagy, Z.
Szolgay, P.
Laviniu, T.
Gacsadi, A.
机构：
[1] Univ Szeged, Inst Informat, H-6701 Szeged, Hungary
[2] Univ Pannonia Veszprem, Dept Elect Engn, H-8200 Veszprem, Hungary
来源：
2012 13TH INTERNATIONAL WORKSHOP ON CELLULAR NANOSCALE NETWORKS AND THEIR APPLICATIONS (CNNA) | 2012年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper an image correlation algorithm is implemented on FPGA architecture for assisted movements of visually impaired persons or automotive driving systems. Taking into account the limitations of FPGA devices and the special requirements of the correlation based image matching algorithm a semi-parallel approach is proposed. This provides an optimal trade-off between area and speed of the implemented algorithm. Several key issues are investigated and discussed related to the speed and area.
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页数：5
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