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Thermal Analysis of Embedded Chip

被引：0
|
作者：
San, Lee Pik [1 ]
Eu, Ong Kang [2 ]
Azid, Ishak Abdul [1 ]
机构：
[1] USM Engn Campus, Sch Mech Engn, Nibong Tebal 14300, Pulau Pinang, Malaysia
[2] Intel Technol Malaysia, Kedah Darul Aman 09000, Malaysia
来源：
2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT) | 2012年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
Embedded structure of chip has created issues of thermo-mechanical reliability which is a great concern in electronic industries nowadays. Embedded structure that consists of components with different Coefficient of Thermal expansion (CTE) may lead to failure because of the heat dissipations performance and CTE mismatch. Therefore, in this paper, finite element analysis is carried out using ABAQUS to investigate the effect of chip thickness and substrate on failure under one cycle of thermal cycling load. Modified Coffin- Manson relation is used to predict fatigue life of copper trace which has the highest Von Mises stress in the model. Thermo- mechanical reliability is determined by comparing fatigue life of the models. Reliability of embedded chip is higher if the fatigue life is longer. It was found that greater thickness of silicon chip will lead to lower fatigue life and less reliable. Besides, higher difference of CTE between substrate materials and copper trace has lower fatigue life. However, thermal conductivity of the substrate material has to be taken into consideration because it can improve heat dissipations performance and this improves reliability of embedded chip.
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页数：6
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