Edge and data adaptive equalization of serial-link transceivers

被引：28

作者：

Wong, Koon-Lun Jackie ^{[1
]}

Chen, E-Hung ^{[2
]}

Yang, Chih-Kong Ken ^{[2
]}

机构：

[1] Broadcom Corp, Irvine, CA 92617 USA

[2] Univ Calif Los Angeles, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 09期

关键词：

bit-error rate; CDR; equalizer; I/O link; ISI; LMS adaptation;

D O I：

10.1109/JSSC.2008.2001876

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Limited channel bandwidth introduces inter-symbol interference (ISI) at both data and edge samples. In addition to the ISI at data samples, ISI at the edge samples (edge ISI) increases the bit error rate (BER) by degrading on the eye diagram and increasing the jitter of the clock and data recovery (CDR). This work proposes a forward FIR equalizer and a decision-feedback equalizer (DFE) that compensate for both data and edge samples. To adapt both the data and edge equalizers, a modified LMS adaptation algorithm is introduced to achieve convergence. A transmitter and receiver are implemented in 0.13 mu m and 0.18 mu m technologies respectively. The edge ISI is improved by 20% and the jitter is improved by 10% in measurement. The link operates over a 120 '' FR4 channel with 24 dB attenuation at Nyquist frequency, and the BER is below 10(-14) at 3.6 Gb/s.

引用

页码：2157 / 2169

页数：13

共 50 条

[31] An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture
Meher, Manas Ranjan
Jong, Ching Chuen
Chang, Chip-Hong
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (12) : 2945 - 2955
[32] A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
Kim, J
Yang, J
Byun, S
Jun, H
Park, J
Conroy, CSG
Kim, B
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (02) : 462 - 471
[33] A PAM-4 Adaptive Analog Equalizer with Decoupling Control Loops for 25-Gb/s CMOS Serial-Link Receiver
Li, Shunbin
Liu, Peng
Wang, Weidong
Fang, Xing
Wu, Dong
Xie, Xianghui
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 221 - 226
[34] A force display system using a serial-link structure driven by a parallel-wire mechanism
Kino, H
Yabe, S
Kawamura, S
ADVANCED ROBOTICS, 2005, 19 (01) : 21 - 37
[35] Fully integrated serial-link receiver with optical interface for long-haul display interconnects
Park, K. -Y.
Oh, W. -S.
Lee, Y. -S.
Choi, W. -Y.
IET CIRCUITS DEVICES & SYSTEMS, 2012, 6 (06) : 375 - 385
[36] A novel method to identify DH parameters of the rigid serial-link robot based on a geometry model
Zhang, Tao
Song, Yuntao
Wu, Huapeng
Wang, Qi
INDUSTRIAL ROBOT-THE INTERNATIONAL JOURNAL OF ROBOTICS RESEARCH AND APPLICATION, 2021, 48 (01): : 157 - 167
[37] An Analytic Approach to Converting POE Parameters Into D-H Parameters for Serial-Link Robots
Wu, Liao
Crawford, Ross
Roberts, Jonathan
IEEE ROBOTICS AND AUTOMATION LETTERS, 2017, 2 (04): : 2174 - 2179
[38] Multi-Valued Signal Generation and Measurement for PAM-4 Serial-Link Test
Sato, Natsuki
Chigira, Takahito
Toyoda, Kohei
Iijima, Yosuke
Yuminaka, Yasushi
2018 IEEE 48TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2018), 2018, : 210 - 214
[39] A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization
Kalantari, Nader
Buckwalter, James F.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2013, 60 (11) : 2920 - 2931
[40] Validating the Performance of a 32nm CMOS High Speed Serial Link Receiver with Adaptive Equalization and Baud-Rate Clock Data Recovery
Puligundla, Sudeep
Spagna, Fulvio
Chen, Lidong
Tran, Amanda
INTERNATIONAL TEST CONFERENCE 2010, 2010,

← 1 2 3 4 5 →