A new fast DCT algorithm and its systolic VLSI implementation

被引：14

作者：

Chang, YT

Wang, CL

机构：

[1] Department of Electrical Engineering, National Tsing Hua University

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1997年 / 44卷 / 11期

关键词：

discrete cosine transform; fast algorithm; matrix-vector multiplication; systolic array; VLSI;

D O I：

10.1109/82.644050

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a new fast algorithm along with its systolic array implementation fur computing the N-point discrete cosine transform (DCT), where N is a power of two. The architecture requires log(2)N multipliers and can evaluate one complete N-point DCT (i.e., N transform samples) every N clock cycles. Due to the features of regularity and modularity, it is well suited to VLSI implementation. As compared to existing systolic DCT designs with the same throughput performance, the proposed one involves much less hardware complexity.

引用

页码：959 / 962

页数：4

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