Formal Guarantees for Localized Bug Fixes

被引:3
|
作者
Mitra, Srobona [1 ]
Banerjee, Ansuman [2 ]
Dasgupta, Pallab [1 ]
Ghosh, Priyankar [1 ]
Kumar, Harish [3 ]
机构
[1] IIT Kharagpur, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India
[2] Indian Stat Inst, Adv Comp & Microelect Unit, Kolkata 700108, India
[3] Intel Technol India Pvt Ltd, Bangalore 560017, Karnataka, India
关键词
Debugging; dynamic slicing; hardware verification; satisfiability; BOUNDED MODEL CHECKING;
D O I
10.1109/TCAD.2013.2252055
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Bug traces produced in simulation serve as the basis for patching the RTL code in order to fix a bug. It is important to prove that the patch covers all instances of the bug scenario; otherwise, the bug may return with a different valuation of the variables involved in the bug scenario. For large circuits, formal methods do not scale well enough to comprehensively eliminate the bug, and achieving adequate coverage in simulation and regression testing becomes expensive. This paper proposes formal methods for analyzing the control trace leading to the observed manifestation of the bug and verifying the robustness of the bug fix with respect to that control trace. We propose a classification of the bug fix based on the guarantee that our analysis can provide about the quality of the bug fix. Our method also prescribes the types of tests that are recommended to validate the bug fix on other types of scenarios. Since our methods are more scalable by orders of magnitude than model checking the entire design, we believe that the proposed formal methods hold immense promise in analyzing bug fixes in practice.
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页码:1274 / 1287
页数:14
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