1V Supply 16-Bit Second Order Sigma-Delta Modulator in a 90nm CMOS Process

被引：0

作者：

Amistoso, Rochelle Marie F. ^{[1
]}

Bautista, Michael Joe A. ^{[1
]}

Delos Santos, Rafael Karlo D. P. ^{[1
]}

Ortiz, Joana Rochelle R. ^{[1
]}

Alarcon, Louis P. ^{[1
]}

Ballesil-Alvarez, Anastacia ^{[1
]}

Hizon, Richard E. ^{[1
]}

机构：

[1] Intel Microprocessors Lab, Santa Clara, CA 95054 USA

来源：

TENCON 2012 - 2012 IEEE REGION 10 CONFERENCE: SUSTAINABLE DEVELOPMENT THROUGH HUMANITARIAN TECHNOLOGY | 2012年

关键词：

Sigma-Delta modulator; OTA integrator; comparator; DAC; latch; filter; decimator;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a second order Sigma-Delta modulator using a 1V dual supply in 90nm technology. The schematic modulator design achieves a signal-to-noise ratio (SNR) of 96.7 dB or 15.7 bits. A gain boosted fully differential folded cascode operational transconductance amplifier (OTA) with a switched capacitor common-mode feedback circuit is implemented as the integrator. The OTA design is able to achieve a 500 V/V DC gain, with a 400mV output swing, Gain Bandwidth (GBW) of 303.5 MHz and a phase margin of 50.9 degrees. A fully-differential preamplifier-based latched comparator is also implemented, achieving a rail-to-rail output and a sensitivity of 10 mu V. Data presented from each of the blocks are from post-layout simulations.

引用

页数：4

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