Multi-protocol embedded PCSIP in a FPGA-SOC

被引：0

作者：

Venkata, R ^{[1
]}

Chan, VS ^{[1
]}

Ton, B ^{[1
]}

Lee, C ^{[1
]}

Ngo, H ^{[1
]}

Kabani, M ^{[1
]}

Nguyen, T ^{[1
]}

Zaliznyak, A ^{[1
]}

Xue, N ^{[1
]}

Shen, S ^{[1
]}

Zheng, M ^{[1
]}

Lai, M ^{[1
]}

Park, S ^{[1
]}

Chan, LN ^{[1
]}

Vijayaraghavan, D ^{[1
]}

Lam, J ^{[1
]}

Patel, R ^{[1
]}

机构：

[1] Altera Corp, San Jose, CA 95134 USA

来源：

CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The configuration space of the Hard IP had to be bounded intelligently. Major architectural enhancements were necessary instead of a simple performance upgrade of the previous Hard IP. Verification complexity mandated design and verification re-use. Emulation and vendor soft IF interoperability testing was another strategy employed for first silicon success.

引用

页码：783 / 786

页数：4

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