Comparative Study of Comparator and Encoder in a 4-bit Flash ADC using 0.18μm CMOS Technology

This paper describes a comparative study of comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the conventional comparator is replaced with an open loop comparator and the non-ROM type encoder is used as the alternative for the conventional encoder. It is implemented using 0.18 mu m CMOS technology. Generally, the Silvaco Electronic Design Automation (EDA) tools is used for drawing the schematics, do the simulations and designing the layout of the proposed Flash ADC. The simulation results include 1.8V analog input range and 24.2662 mW of power dissipation at maximum sampling frequency of 500MHz with the lowest propagation delay time of 539.61ps.