Improvement of power supply rejection ratio of LDO deteriorated by reducing power consumption

被引：5
|
作者：
Heng, Socheat [1 ]
Pham, Cong-Kha [1 ]
机构：
[1] Univ Electrocommun, Dept Elect Engn, Tokyo, Japan
来源：
2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2008年
关键词：
D O I：
10.1109/ICICDT.2008.4567242
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power, consumption is proposed. Designing with 0.25 mu m CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the conventional circuit. It is confirmed that about 40[dB] at 10[Hz] frequency and 20[dB] at 1[kHz] frequency of PSRR are together improved.
引用
收藏
页码：43 / 46
页数：4
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