共 46 条
- [3] Multi-site collaboration in system on chip design and validation: The Intel experience [J]. PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 1 - 1
- [6] On-chip test infrastructure design for optimal multi-site testing of system chips [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 44 - 49
- [8] Assessing Delayed Effects of a Multi-Site System Intervention for Homeless Persons with Serious Mental Illness [J]. Administration and Policy in Mental Health and Mental Health Services Research, 2006, 33 : 115 - 121