A Calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s Four-Stage Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

被引：0

作者：

Lim, Yong ^{[1
,2
]}

Flynn, Michael P. ^{[1
]}

机构：

[1] Univ Michigan, Ann Arbor, MI 48109 USA

[2] Samsung Elect, Yongin, South Korea

来源：

2017 SYMPOSIUM ON VLSI CIRCUITS | 2017年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is applied in a 15b, 100 MS/s calibration-free SAR-assisted pipeline ADC. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. The ADC achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in a SNDR based Schreier FoM of 176.6 dB.

引用

页码：C98 / C99

页数：2