共 50 条
- [12] A VLSI Implementation of Double Precision Floating-Point Logarithmic Function [J]. 2019 IEEE 4TH INTERNATIONAL CONFERENCE ON SIGNAL AND IMAGE PROCESSING (ICSIP 2019), 2019, : 345 - 349
- [13] High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2018, 12 (01): : 20 - 29
- [14] An FPGA implementation of a fully verified double precision IEEE floating-point adder [J]. 2007 IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, 2007, : 83 - 88
- [15] Low-Latency Double-Precision Floating-Point Division for FPGAs [J]. PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2014, : 107 - 114
- [16] Reaping the processing potential of FPGA on double-precision floating-point operations: an eigenvalue solver case study [J]. 2010 18TH IEEE ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2010), 2010, : 95 - 102
- [17] Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2017, 11 (04): : 149 - 158
- [18] A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers [J]. IEEE ACCESS, 2020, 8 : 165740 - 165747