Threshold voltage model for MOSFETs with high-K gate dielectrics

被引：21
|
作者：
Liu, XY [1 ]
Kang, JF [1 ]
Sun, L [1 ]
Han, RQ [1 ]
Wang, YY [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
IEEE ELECTRON DEVICE LETTERS | 2002年 / 23卷 / 05期
关键词：
gate insulator; high-K gate dielectric; MOSFET; threshold voltage; short channel effect;
D O I：
10.1109/55.998873
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An analytic threshold voltage model, which can account for the short channel effect and the fringing field effect of sub-100 run high-K gate dielectrics MOSFETs, has been developed. The model considers the two-dimensional (2-D) effect both in silicon bulk and in gate dielectric layer. The results of the model are consistent with 2-D numerical simulation results.
引用
收藏
页码：270 / 272
页数：3
相关论文
共 50 条
  • [21] Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning
    Kirsch, P. D.
    Sivasubramani, P.
    Huang, J.
    Young, C. D.
    Park, C. S.
    Freeman, K.
    Hussain, M. M.
    Bersuker, G.
    Harris, H. R.
    Majhi, P.
    Lysaght, P.
    Tseng, H. -H.
    Lee, B. H.
    Jammy, R.
    ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 269 - +
  • [22] Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics
    Hakim, MMA
    Haque, A
    SOLID-STATE ELECTRONICS, 2004, 48 (07) : 1095 - 1100
  • [23] Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics
    Matsuo, K
    Saito, T
    Yagishita, A
    Iinuma, T
    Murakoshi, A
    Nakajima, K
    Omoto, S
    Suguro, K
    2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 70 - 71
  • [24] Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics
    Rana, Ashwani K.
    Chand, Narottam
    Kapoor, Vinod
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2010, 5 (03) : 343 - 348
  • [25] High-K dielectrics for the gate stack
    Locquet, Jean-Pierre
    Marchiori, Chiara
    Sousa, Maryline
    Fompeyrine, Jean
    Seo, Jin Won
    Journal of Applied Physics, 2006, 100 (05):
  • [26] High-K dielectrics for the gate stack
    Locquet, Jean-Pierre
    Marchiori, Chiara
    Sousa, Maryline
    Fompeyrine, Jean
    Seo, Jin Won
    JOURNAL OF APPLIED PHYSICS, 2006, 100 (05)
  • [27] Low voltage SILC Analysis for High-k/Metal Gate Dielectrics
    Rahim, N.
    Misra, D.
    ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 283 - 287
  • [28] Threshold voltage instabilities in high-k gate dielectric stacks
    Zafar, S
    Kumar, A
    Gusev, E
    Cartier, E
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (01) : 45 - 64
  • [29] An analytical surface potential and threshold voltage model of fully depleted strained-SOI MOSFETs in Nanoscale with high-k gate oxide
    Pradhan, Kumar Prasannajit
    Mohapatra, Sushanta Kumar
    Sahu, Prasanna Kumar
    2012 1ST INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGY TRENDS IN ELECTRONICS, COMMUNICATION AND NETWORKING (ET2ECN), 2012,
  • [30] Drain Current - Drain Voltage Relation for MOSFETs with High-k Gate Stacks
    Kar, Samares
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 9, 2011, 41 (03): : 389 - 400
12345