Fully-parallel VLSI implementation of vector quantization processor using neuron-MOS technology

被引:0
|
作者
Nakada, A
Konda, M
Morimoto, T
Yonezawa, T
Shibata, T [1 ]
Ohmi, T
机构
[1] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 1138656, Japan
[2] Tohoku Univ, Grad Sch Engn, Dept Elect Engn, Sendai, Miyagi 9808579, Japan
[3] Univ Tokyo, Sch Frontier Sci, Dept Frontier Informat, Tokyo 1138656, Japan
[4] Tohoku Univ, New Ind Creat Hatchery Ctr, Sendai, Miyagi 9808579, Japan
关键词
vector quantization; winner-take-all; neuron MOS; image compression; analog LSI;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An analog vector quantization processor has been designed based on the neuron-MOS (vMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the vMOS ROM. technology. A new-architecture vMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-mu m double-polysilicon CMOS technology with the chip size of 7.2 mm x 7.2 mm, and the basic operation of the circuits has been demonstrated.
引用
收藏
页码:1730 / 1738
页数:9
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