Parallel genetic algorithm for VLSI building block layout

被引：0
|
作者：
Xu, Ning [1 ]
Huang, Feng [1 ]
Jiang, Zhonghua [1 ]
机构：
[1] Wuhan Univ Technol, Wuhan 430070, Peoples R China
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-4 | 2006年
关键词：
building block layout; parallel genetic algorithms; physical design;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The VLSI building block layout(BBL) becomes a more and more important problem for VLSI physical design. In this paper, A Multithread scheme for parallelizing a genetic algorithm for BBL placement optimization is presented. The parallel genetic algorithms(PGA) are realized, using sequence-pair(SP) as the representation. Parallel. algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutions to a problem. Our experimental results on a SUN workstation with 4 CPUs have shown that the scheme is effective in improving performance of placement over that of a sequential implementation.
引用
收藏
页码：675 / 678
页数：4
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