Parallel genetic algorithm for VLSI building block layout

被引：0
|
作者：
Xu, Ning [1 ]
Huang, Feng [1 ]
Jiang, Zhonghua [1 ]
机构：
[1] Wuhan Univ Technol, Wuhan 430070, Peoples R China
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-4 | 2006年
关键词：
building block layout; parallel genetic algorithms; physical design;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The VLSI building block layout(BBL) becomes a more and more important problem for VLSI physical design. In this paper, A Multithread scheme for parallelizing a genetic algorithm for BBL placement optimization is presented. The parallel genetic algorithms(PGA) are realized, using sequence-pair(SP) as the representation. Parallel. algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutions to a problem. Our experimental results on a SUN workstation with 4 CPUs have shown that the scheme is effective in improving performance of placement over that of a sequential implementation.
引用
收藏
页码：675 / 678
页数：4
相关论文
共 50 条
  • [1] Stochastic parallel algorithm and its applications to VLSI layout
    Qiao, Changge
    Gao, Deyuan
    Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 1994, 12 (01): : 74 - 78
  • [2] Pin assignment with global routing for VLSI building block layout
    Hiroshima Univ, Higashi-Hiroshima, Japan
    IEEE Trans Comput Aided Des Integr Circuits Syst, 12 (1575-1583):
  • [3] CHANNEL SWITCHBOX DEFINITION FOR VLSI BUILDING-BLOCK LAYOUT
    YANG, C
    WONG, DF
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (12) : 1485 - 1493
  • [4] Pin assignment with global routing for VLSI building block layout
    Koide, T
    Wakabayashi, S
    Yoshida, N
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (12) : 1575 - 1583
  • [5] VLSI processor of parallel genetic algorithm
    Choi, YH
    Chung, DJ
    PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS, 2000, : 143 - 146
  • [6] A fast algorithm for VLSI building block placement
    Xu, Ning
    Huang, Feng
    Jiang, Zhonghua
    2006 IMACS: MULTICONFERENCE ON COMPUTATIONAL ENGINEERING IN SYSTEMS APPLICATIONS, VOLS 1 AND 2, 2006, : 2157 - +
  • [7] Hybrid genetic algorithm for VLSI macro cell layout
    Sathiamoorthy, S
    Andaljayalakshmi, G
    SOFT COMPUTING AND INDUSTRY: RECENT APPLICATIONS, 2002, : 791 - 798
  • [8] Building block layout by parallel simulated annealing algorithms
    Luo, QL
    Hong, XL
    Dong, SQ
    Zhou, Q
    2004 INTERNATIONAL CONFERENCE ON COMMUNICATION, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEMS - VOL 2: SIGNAL PROCESSING, CIRCUITS AND SYSTEMS, 2004, : 1262 - 1265
  • [9] Block layout method in the block stockyard based on the genetic algorithm
    Roh, Myung-Il
    OCEAN SYSTEMS ENGINEERING-AN INTERNATIONAL JOURNAL, 2012, 2 (04): : 271 - 287
  • [10] A FLOORPLANNING METHOD WITH TOPOLOGICAL CONSTRAINT MANIPULATION IN VLSI BUILDING-BLOCK LAYOUT
    KOIDE, T
    KATSURA, Y
    YAMATANI, K
    WAKABAYASHI, S
    YOSHIDA, N
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1994, E77A (12) : 2053 - 2057
12345