A Scalable, Low Voltage, Low Cost SONOS Memory Technology For Embedded NVM Applications

被引：0

作者：

Ramkumar, K. ^{[1
]}

Kouznetsov, I. ^{[1
]}

Prabhakar, V. ^{[1
]}

Shakeri, K. ^{[1
]}

Yu, X. ^{[1
]}

Shih, P. C. ^{[2
]}

Huang, C. C. ^{[2
]}

Lee, H. C. ^{[2
]}

Wu, S. H. ^{[2
]}

Gau, J. H. ^{[2
]}

Yang, Y. ^{[1
]}

Hinh, L. ^{[1
]}

Lee, S. ^{[1
]}

Samanta, S. ^{[1
]}

Shih, H. M. ^{[1
]}

Geha, S. ^{[1
]}

Sheu, Y. K. ^{[1
,2
]}

机构：

[1] Cypress Semicond Inc, San Jose, CA 95134 USA

[2] United Microelect Corp, Tainan, Taiwan

来源：

2013 5TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW) | 2013年

关键词：

SONOS; embedded; NVM; Reliability;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A novel low cost, eNVM technology is presented which has the lowest program/erase voltage reported to date. It is based on the integration of a SONOS based NVM module into a foundry CMOS process with only 3 additional masks and no additional HV oxide. An optimized integration scheme ensures that the CMOS device parameters of the eNVM process are closely matched to baseline process. Even with the low 7.5V program/erase voltage, excellent reliability has been demonstrated meeting automotive data retention requirements and 100k cycle endurance on a 4.5Mbit flash memory macro.

引用

页码：199 / 202

页数：4

共 50 条

[31] A low-cost SiGe:C BiCMOS technology with embedded flash memory and complementary LDMOS module
Knoll, D
Fox, A
Ehwald, KE
Heinemann, B
Barth, R
Fischer, A
Rücker, H
Schley, P
Scholz, R
Korndörfer, F
Senapati, B
Stikanov, VE
Tillack, B
Winkler, W
Wolf, C
Zaumseil, P
Proceedings of the 2005 BIPOLAR/BiCMOS Circuits and Technology Meeting, 2005, : 132 - 135
[32] A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs
Trentzsch, M.
Flachowsky, S.
Richter, R.
Paul, J.
Reimer, B.
Utess, D.
Jansen, S.
Mulaosmanovic, H.
Mueller, S.
Slesazeck, S.
Ocker, J.
Noack, M.
Mueller, J.
Polakowski, P.
Schreiter, J.
Beyer, S.
Mikolajick, T.
Rice, B.
2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,
[33] CMOS device and interconnect technology enhancements for low power low voltage applications
Vasudev, PK
SOLID-STATE ELECTRONICS, 1996, 39 (04) : 481 - 488
[34] Low Latency and Low Cost Smart Embedded Seismograph for Early Warning IoT Applications
Germenis, N.
Fountas, P.
Koulamas, C.
2020 9TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2020, : 129 - 132
[35] A Low-Cost Scalable Voltage-Frequency Adjustor for Implementing Low-Power Systems
Cheng, Ching-Hwa
Hsu, Sheng-Wei
Guo, Jiun-In
2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 655 - 658
[36] Low-Cost Embedded System Applications for Smart Cities
Herrera, Victoria Alejandra Salazar
de Araujo, Hugo Puertas
Penteado, Cesar Giacomini
Gazziro, Mario
Carmo, Joao Paulo
BIG DATA AND COGNITIVE COMPUTING, 2025, 9 (02)
[37] Embedded genetic algorithm for low-power, low-cost, and low-size-memory devices
Medeiros, Denis R. da S.
Torquato, Matheus F.
Fernandes, Marcelo A. C.
ENGINEERING REPORTS, 2020, 2 (09)
[38] Special and embedded memory macrocells for low-cost and low-power in MPEG environment
Hara, H
Matsui, M
Otomo, G
Seta, K
Sakurai, T
IEICE TRANSACTIONS ON ELECTRONICS, 1996, E79C (06) : 750 - 756
[39] A scalable SOI technology for three successive generations: 0.18, 0.13 and 0.1 mu m for low-voltage and low-power applications
Pelloie, JL
Faynot, O
Raynaud, C
Dunne, B
Martin, F
Tedesco, S
Hartmann, J
1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 118 - 119
[40] Low-cost, scalable, and automated fluid sampling for fluidics applications
Booeshaghi, A. Sina
Kil, Yeokyoung
Min, Kyung Hoi
Gehring, Jase
Pachter, Lior
HARDWAREX, 2021, 10

← 1 2 3 4 5 →