Process-induced charge trapping and junction breakdown instability in deep trench isolation for high voltage Smart Power IC process

被引:0
|
作者
Kim, Hee-dae [1 ]
Park, Ju-won [1 ]
Ko, Choul-Joo [1 ]
Jun, Bon-Keun [1 ]
Moon, Namchil [1 ]
Kwon, KyungWook [1 ]
Lee, Changjun [1 ]
Sung, Kunsik [1 ]
Kim, Nam-Joo [1 ]
Yoo, Kwang-Dong [1 ]
Lee, Yoon-Jong [1 ]
机构
[1] Dongbu Hitek, Analog Foundry Proc Dev Team, Puchon 420712, Gyeonggi Do, South Korea
关键词
DTI(Deep Trench Isolation); Avalanche junction breakdown; Charge trapping; Walkout;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In BCD process for high voltage Smart Power IC, junction breakdown instability in DTI(Deep Trench Isolation) process is strongly depend on the process-induced mechanical stress and DTI test pattern shape. The DTI test pattern with sharp corner generates larger charge trap density and larger breakdown voltage shift than that of round corner test pattern. Through 3D TCAD simulation and SEM/TEM analysis, we noticed that sharp corner type has higher process-induced mechanical stress and more silicon dislocation defect than that of round corner type.
引用
收藏
页数:4
相关论文
共 25 条
  • [21] Impact of damage-free wet etching process on fabrication of high breakdown voltage GaN p-n junction diodes
    Asai, Naomi
    Ohta, Hiroshi
    Horikiri, Fumimasa
    Narita, Yoshinobu
    Yoshida, Takehiro
    Mishima, Tomoyoshi
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2019, 58 (SC)
  • [22] A High Power Driver IC for Electroluminescent Panel: Design Challenges and Advantages of using the Emerging LEES-SMART GaN-on-CMOS process
    Jia, Zhou
    Ge, Tong
    Guo, Linfei
    Eileen, Ng Pei Jian
    He, Huiqiao
    Chang, Joseph
    INTERNATIONAL CONFERENCE ON MATERIALS FOR ADVANCED TECHNOLOGIES (ICMAT2015) - SYMPOSIUM B, N, U, W, Z, 2016, 141 : 91 - 93
  • [23] The Effect of Process-Induced Porosity on Fatigue Properties of Ti6Al4V Alloy via High-Power Direct Energy Deposition
    Lv, Hang
    Zhang, Zhenlin
    Li, Junjie
    Liu, Yan
    Chen, Hui
    He, Huabing
    Cheng, Jing
    Chen, Yong
    COATINGS, 2022, 12 (06)
  • [24] Deep Insight into Process-induced Pre-existing Traps and PBTI Stress-induced Trap Generations in High-k Gate Dielectrics through Systematic RTN Characterizations and Ab initio Calculations
    Chen, Jiezhi
    Nakasaki, Yasushi
    Mitani, Yuichiro
    2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2016,
  • [25] High-Breakdown-Voltage and Low-Specific-on-Resistance GaN p-n Junction Diodes on Free-Standing GaN Substrates Fabricated Through Low-Damage Field-Plate Process
    Hatakeyama, Yoshitomo
    Nomoto, Kazuki
    Terano, Akihisa
    Kaneda, Naoki
    Tsuchiya, Tadayoshi
    Mishima, Tomoyoshi
    Nakamura, Tohru
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (02)