Design considerations for CMOS near the limits of scaling

被引：35
|
作者：
Frank, DJ [1 ]
Taur, Y [1 ]
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
SOLID-STATE ELECTRONICS | 2002年 / 46卷 / 03期
关键词：
CMOS; scaling limits; tunneling currents; power dissipation; MOSFET design;
D O I：
10.1016/S0038-1101(01)00102-2
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As MOSFETs reach the limits of scaling, a variety of physical and application-related constraints must be considered. This paper provides an overview of these constraints for conventional bulk-like MOSFET design, including two-dimensional effects due to short-channel length, tunneling currents through thin insulators and junctions, limitations on supply and threshold voltage reduction, dopant fluctuation effects, and overall system power dissipation requirements. We show that the end of scaling is different for different applications, depending especially on the leakage dissipation constraints. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：315 / 320
页数：6
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