A PCI bus based correlation matrix memory and its application to k-NN classification

被引：3

作者：

Zhou, P ^{[1
]}

Austin, J ^{[1
]}

机构：

[1] Univ York, Dept Comp Sci, Adv Comp Architecture Grp, York YO10 5DD, N Yorkshire, England

来源：

PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS FOR NEURAL, FUZZY AND BIO-INSPIRED SYSTEMS, MICORNEURO'99 | 1999年

关键词：

D O I：

10.1109/MN.1999.758864

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes a PCI bus based implementation of a binary correlation matrix memory (CMM) neural network and its application and performance for use as a k-NN based pattern classification system. The system expands on earlier VME based system incorporating FPGA based implementation through greater integration and lower cost. Experimental results for several benchmarks show that, compared with a simple k-NN method, rile CMM hardware gave speed Icp of 8-98.8 times during recall process with a classification performance,which is 99%-100% that of a conventional k-NN implementation.

引用

页码：196 / 204

页数：9

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