PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems

被引:7
|
作者
Al-hayanni, Mohammed A. Noaman [1 ,2 ]
Rafiev, Ashur [3 ,4 ]
Xia, Fei [4 ]
Shafik, Rishad [5 ]
Romanovsky, Alexander [3 ]
Yakovlev, Alex [1 ]
机构
[1] Newcastle Univ, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
[2] Univ Technol Baghdad, Dept Elect Engn, Baghdad 10001, Iraq
[3] Newcastle Univ, Sch Comp, Newcastle Upon Tyne, Tyne & Wear, England
[4] Newcastle Univ, Sch Engn, Newcastle Upon Tyne, Tyne & Wear, England
[5] Newcastle Univ, Elect Syst, Newcastle Upon Tyne, Tyne & Wear, England
基金
英国工程与自然科学研究理事会;
关键词
IP networks; Computational modeling; Hardware; System performance; Optimization; Measurement; Monitoring; Run-time management; many-core; speedup; power modelling; energy-delay-product; energy per instruction; POWER; PERFORMANCE; VOLTAGE;
D O I
10.1109/TC.2020.2975787
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Performance and energy efficiency considerations have shifted computing paradigms from single-core to many-core architectures. At the same time, traditional speedup models such as Amdahl's Law face challenges in the run-time reasoning for system performance and energy efficiency, because these models typically assume limited variations of the parallel fraction. Moreover, the parallel fraction, which varies dynamically in workloads, is generally unknown at run-time without application-level instrumentation. This article describes novel performance/energy trade-off models based on realistic architectural considerations, which describe the parallel fraction and speedup as functions of performance counter values available in modern processors, removing the need for application-level instrumentation. These are then used to develop a Parallelization-Aware Run-time Management (PARMA) approach. PARMA aims at controlling core allocations and operating voltage/frequency points for energy efficiency, according to the varying workload parallel fractions. The efficacy of our models and the PARMA approach is extensively validated using a number of PARSEC benchmark applications, involving two performance/energy trade-off metrics: energy-delay-product (EDP), typically used in high-performance applications and energy per instruction (EPI), suitable for energy-aware applications. Up to 48 and 68 percent improvements in EDP and EPI have been observed using the PARMA approach compared with parallelization-agnostic methods.
引用
收藏
页码:1507 / 1518
页数:12
相关论文
共 50 条
  • [41] PyDac: A Resilient Run-Time Framework for Divide-and-Conquer Applications on a Heterogeneous Many-Core Architecture
    Huang, Bin
    Sass, Ron
    DeBardeleben, Nathan
    Blanchard, Sean
    [J]. EURO-PAR 2013: PARALLEL PROCESSING WORKSHOPS, 2014, 8374 : 845 - 854
  • [42] Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array
    Stillmaker, Aaron
    Stillmaker, Lucas
    Baas, Bevan
    [J]. PROCEEDINGS OF THE 2012 IEEE 18TH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS 2012), 2012, : 652 - 659
  • [43] Special issue on energy-efficient many-core embedded systems and architectures (SI:NoCArc18)
    Palesi, Maurizio
    Chen, Kun-Chih
    Reshadi, Midia
    [J]. JOURNAL OF SYSTEMS ARCHITECTURE, 2020, 109
  • [44] Efficient Parallelization of a Genetic Algorithm Solution on the Traveling Salesman Problem with Multi-core and Many-core Systems
    Abbasi, M.
    Rafiee, M.
    [J]. INTERNATIONAL JOURNAL OF ENGINEERING, 2020, 33 (07): : 1257 - 1265
  • [45] Run-time Exploitation of Application Dynamism for Energy-efficient Exascale Computing (READEX)
    Oleynik, Yury
    Gerndt, Michael
    Schuchart, Joseph
    Kjeldsberg, Per Gunnar
    Nagel, Wolfgang E.
    [J]. 2015 IEEE 18TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND ENGINEERING (CSE), 2015, : 347 - +
  • [46] Run-Time Management for Multicore Embedded Systems With Energy Harvesting
    Xiang, Yi
    Pasricha, Sudeep
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (12) : 2876 - 2889
  • [47] The Agamid design-space exploration frameworkTask-accurate simulation of hardware-enhanced run-time management for many-core
    Daniel Gregorek
    Alberto Garcia-Ortiz
    [J]. Design Automation for Embedded Systems, 2018, 22 : 293 - 314
  • [48] Design of Many-Core Big Little μBrains for Energy-Efficient Embedded Neuromorphic Computing
    Varshika, M. Lakshmi
    Balaji, Marsha
    Corradi, Federico
    Das, Anup
    Stuijt, Jan
    Catthoor, Francky
    [J]. PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, : 1011 - 1016
  • [49] EENet: Energy Efficient Neural Networks with Run-time Power Management
    Li, Xiangjie
    Shen, Yingtao
    Zou, An
    Ma, Yehan
    [J]. 2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC, 2023,
  • [50] Variability-Aware Dark Silicon Management in On-Chip Many-Core Systems
    Shafique, Muhammad
    Gnad, Dennis
    Garg, Siddharth
    Henkel, Joerg
    [J]. 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 387 - 392