A New Approach and Tool in Verifying Asynchronous Circuits

被引：0

作者：

Nguyen, Tin T. ^{[1
]}

Khoi-Nguyen Le-Huu ^{[1
]}

Bui, Thang H. ^{[1
]}

Anh-Vu Dinh-Duc ^{[1
]}

机构：

[1] Ho Chi Minh City Univ Technol, Ho Chi Minh City, Vietnam

来源：

2012 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC 2012) | 2012年

关键词：

SYMBOLIC MODEL CHECKING; VERIFICATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

EDA tools have been considered long time ago in hardware design. Some tools have also been proposed for asynchronous circuits, an emerged approach to overcome the clock distribution problem, the main drawback of synchronous circuits. However, they are lack of methods for verifying the correctness of the produced circuits. This work is about a new version of the PAiD tool developed at HCMC University of Technology that can enable engineers to design, verify and synthesize asynchronous circuits. Experiments in verifying circuits have been also provided in this work.

引用

页码：152 / 157

页数：6

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