Hybrid Cu and Al interconnects for high-performance system LSI

A high performance 0.18 mu m CMOS logic device has been developed with 0.15 mu m transistor and six level interconnects. Multi-level interconnect system consists of conventional process with Al wire and dual damascene process with Cu wire. It is well known that a reduction of interconnect delay time is important as the design rule is scaled. Recently low resistance Cu interconnects and low-k dielectric materials are expected to solve this problem. We investigated the interconnect delay time of Cu and Al for the fine metal pitch and the coarse metal pitch, to optimize the interconnect system for 0.18 mu m design rule generation. 4-level Al interconnects with fine metal pitch are suitable for short distance wiring such as intra-block cell to cell interconnects, whereas 2-level Cu interconnects with coarse metal pitch are used for long distance wiring such as mega-block to block interconnects to achieve high-speed and high-density system LSI devices.