IEEE 802.3 100Gbps Ethernet PCS IP Design Challenges and Solutions

被引：0

作者：

De Silva, Udara Piumal ^{[1
]}

Lokumarambage, Anusha ^{[1
]}

Malavipathirana, Hasantha ^{[1
]}

Mohottala, Chathuranga ^{[1
]}

Thayaparan, Subramaniam ^{[1
]}

机构：

[1] Univ Moratuwa, Dept Elect & Telecommun Engn, Moratuwa, Sri Lanka

来源：

2016 IEEE SYMPOSIUM ON COMPUTER APPLICATIONS & INDUSTRIAL ELECTRONICS (ISCAIE) | 2016年

关键词：

100 Gbps Ethernet; Physical Coding Sublayer;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper identifies the challenges involved in designing the 100 Gigabit per second (Gbps) Ethernet Physical Coding Sublayer (PCS) Semiconductor Intellectual property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics, implementation challenges and verification challenges. Furthermore, our solutions to identified challenges are presented in the paper.

引用

页码：21 / 25

页数：5

共 28 条

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