Event-driven Simulation of Digital Circuits using Modified Petri Nets Algorithm

被引：0
|
作者：
Lapin, Alexander [1 ]
Bulakh, Dmitry [1 ]
Vagapov, Yuriy [2 ]
机构：
[1] Natl Res Univ Elect Technol, Dept Integrated Circuits Design, Moscow 124498, Russia
[2] Glyndwr Univ, Sch Appl Sci Comp & Engn, Mold Rd, Wrexham LL11 2AW, Wales
来源：
PROCEEDINGS OF THE 2017 7TH INTERNATIONAL CONFERENCE INTERNET TECHNOLOGIES AND APPLICATIONS (ITA) | 2017年
关键词：
design automation; integrated circuit design; event-driven simulation; delta delay; gate level simulation; behavioural simulation; Petri net;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This paper presents a modified Petri nets simulation algorithm applied as an engine for a logic simulator in digital integrated circuit design. The simulator uses an eventdriven algorithm and eliminates the delta delay which occurs in the majority of modern simulation algorithms. The algorithm has been tested for the logic simulation of combinational digital circuits and demonstrated more accurate simulation results. This has been achieved due to solving the issue of the priority choice problem when two or more events are occurring simultaneously.
引用
收藏
页码：15 / 17
页数：3
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