Survey of Scheduling Techniques for Addressing Shared Resources in Multicore Processors

被引:97
|
作者
Zhuravlev, Sergey [1 ]
Carlos Saez, Juan [2 ]
Blagodurov, Sergey [1 ]
Fedorova, Alexandra [1 ]
Prieto, Manuel [2 ]
机构
[1] Simon Fraser Univ, Burnaby, BC V5A 1S6, Canada
[2] Univ Complutense Madrid, ArTeCS Grp, E-28040 Madrid, Spain
基金
加拿大自然科学与工程研究理事会;
关键词
Performance; Measurement; Algorithms; Survey; shared resource contention; thread level scheduling; power-aware scheduling; thermal effects; cooperative resource sharing; CAPACITY ALLOCATION; CACHE; PERFORMANCE; REPLICATION; MANAGEMENT; PLACEMENT; POLICIES; ENERGY;
D O I
10.1145/2379776.2379780
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for modern computing platforms and will most likely continue to be dominant well into the foreseeable future. As with any system, CMPs offer a unique set of challenges. Chief among them is the shared resource contention that results because CMP cores are not independent processors but rather share common resources among cores such as the last level cache (LLC). Shared resource contention can lead to severe and unpredictable performance impact on the threads running on the CMP. Conversely, CMPs offer tremendous opportunities for mulithreaded applications, which can take advantage of simultaneous thread execution as well as fast inter thread data sharing. Many solutions have been proposed to deal with the negative aspects of CMPs and take advantage of the positive. This survey focuses on the subset of these solutions that exclusively make use of OS thread-level scheduling to achieve their goals. These solutions are particularly attractive as they require no changes to hardware and minimal or no changes to the OS. The OS scheduler has expanded well beyond its original role of time-multiplexing threads on a single core into a complex and effective resource manager. This article surveys a multitude of new and exciting work that explores the diverse new roles the OS scheduler can successfully take on.
引用
收藏
页数:28
相关论文
共 50 条
  • [21] Reliability-Aware Scheduling on Heterogeneous Multicore Processors
    Naithani, Ajeya
    Eyerman, Stijn
    Eeckhout, Lieven
    2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2017, : 397 - 408
  • [22] The impact of dynamically heterogeneous multicore processors on thread scheduling
    Bower, Fred A.
    Sorin, Daniel J.
    Cox, Landon P.
    IEEE MICRO, 2008, 28 (03) : 17 - 25
  • [23] Cache Utilization-Aware Scheduling for Multicore Processors
    Chu, Edward T. -H.
    Lu, Wen-wei
    2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2012, : 368 - 371
  • [24] A Survey of Multicore Processors A review of their common attributes
    Blake, Geoffrey
    Dreslinski, Ronald G.
    Mudge, Trevor
    IEEE SIGNAL PROCESSING MAGAZINE, 2009, 26 (06) : 26 - 37
  • [25] Fair memory access scheduling algorithms for multicore processors
    El-Moursy, Ali A.
    El-Reedy, Walid
    Fahmy, Hossam A. H.
    INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS, 2015, 30 (04) : 286 - 308
  • [26] A Fair and Efficient Gang Scheduling Algorithm for Multicore Processors
    Manickam, Viswanathan
    Aravind, Alex
    WIRELESS NETWORKS AND COMPUTATIONAL INTELLIGENCE, ICIP 2012, 2012, 292 : 467 - 476
  • [27] Scheduling multicore workload on shared multipurpose clusters
    Templon, J. A.
    Acosta-Silva, C.
    Flix Molina, J.
    Forti, A. C.
    Perez-Calero Yzquierdo, A.
    Starink, R.
    21ST INTERNATIONAL CONFERENCE ON COMPUTING IN HIGH ENERGY AND NUCLEAR PHYSICS (CHEP2015), PARTS 1-9, 2015, 664
  • [28] Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects
    Akram, Shoaib
    Kumar, Rakesh
    Chen, Deming
    2009 IEEE 7TH SYMPOSIUM ON APPLICATION SPECIFIC PROCESSORS (SASP 2009), 2009, : 7 - 14
  • [29] CacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors
    Evtyushkin, Dmitry
    Panfilov, Peter
    Ponomarev, Dmitry
    PARALLEL COMPUTING TECHNOLOGIES, 2011, 6873 : 284 - +
  • [30] Performance aware shared memory hierarchy model for multicore processors
    Mohamed, Ahmed M.
    Mubark, Nada
    Zagloul, Saad
    SCIENTIFIC REPORTS, 2023, 13 (01):