Impact of line width on hydrostatic stress and stress-induced voiding in Cu interconnects

被引:0
|
作者
Guo, H. Y. [1 ]
Chen, L. [1 ]
机构
[1] Univ Sci & Technol Beijing, Sch Mat Sci & Engn, Beijing 100083, Peoples R China
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Hydrostatic stress of Cu damascene interconnects was calculated by using finite element method in the present work. The analytical work was performed to examine the distribution of hydrostatic stress and the effect of different line width in the Cu interconnects. Then a model of atomic diffusion was presented and used to calculate the size of stress-induced voiding according to result of hydrostatic stress. The results indicate that the stress is highly non-uniform throughout the Cu structure and the highest tensile hydrostatic stress exists on the bottom interface, and the size of stress-induced voiding is strongly dependent upon line width in Cu interconnects.
引用
收藏
页数:4
相关论文
共 50 条
  • [41] Mechanisms of stress-induced voids in multi-level Cu interconnects
    Park, BL
    Hah, SR
    Park, CG
    Jeong, DK
    Son, HS
    Oh, HS
    Chung, JH
    Nam, JL
    Park, KM
    Byun, JD
    PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, : 130 - 132
  • [42] The influence of temperature and dielectric materials on stress induced voiding in Cu dual damascene interconnects
    Gan, ZG
    Shao, W
    Mhaisalkar, SG
    Chen, Z
    Li, HY
    THIN SOLID FILMS, 2006, 504 (1-2) : 161 - 165
  • [43] Stress-induced voiding under vias connected to wide Cu metal leads
    Ogawa, ET
    McPherson, JW
    Rosal, JA
    Dickerson, KJ
    Chiu, TC
    Tsung, LY
    Jain, MK
    Bonifield, TD
    Ondrusek, JC
    McKee, WR
    40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2002, : 312 - 321
  • [44] Effect of via microstructure on Cu/low-k stress-induced voiding
    Lin X.-L.
    Hou T.-X.
    Zhang X.-W.
    Yao R.-H.
    Huanan Ligong Daxue Xuebao/Journal of South China University of Technology (Natural Science), 2011, 39 (03): : 135 - 139
  • [45] Stress and Stress Induced Failure of Damascene Cu Interconnects
    Paik, Jong-Min
    Park, Il-Mok
    Joo, Young-Chang
    ELECTRONIC MATERIALS LETTERS, 2005, 1 (01) : 77 - 85
  • [46] Hydrostatic stress and hydrostatic stress gradients in passivated copper interconnects
    Ang, D.
    Ramanujan, R. V.
    MATERIALS SCIENCE AND ENGINEERING A-STRUCTURAL MATERIALS PROPERTIES MICROSTRUCTURE AND PROCESSING, 2006, 423 (1-2): : 157 - 165
  • [47] Physics-based simulation of stress-induced and electromigration-induced voiding and their interactions in on-chip interconnects
    Kteyan, Armen
    Sukharev, Valeriy
    MICROELECTRONIC ENGINEERING, 2021, 247
  • [48] Numerical characterization of the stress induced voiding inside via of various Cu/Low k interconnects
    Yao, CH
    Huang, TC
    Chi, KS
    Wan, WK
    Lin, HH
    Hsia, CC
    Liang, MS
    PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 24 - 26
  • [49] Critical temperature shift for Stress Induced Voiding in Advanced Cu Interconnects for 32 nm and beyond
    Morusupalli, Rao
    Rao, R.
    Lee, Tae-Kyu
    Shen, Yu-Lin
    Kunz, M.
    Tamura, N.
    Budiman, A. S.
    INTERNATIONAL CONFERENCE ON MATERIALS FOR ADVANCED TECHNOLOGIES (ICMAT2015), SYMPOSIUM C - SOLAR PV (PHOTOVOLTAICS) MATERIALS, MANUFACTURING AND RELIABILITY, 2016, 139 : 32 - 40
  • [50] Novel dielectric slots in Cu interconnects for suppressing stress-induced void failure
    Lim, YK
    Pey, KL
    Tan, JB
    Lee, TJ
    Vigar, D
    Hsia, LC
    Lim, YH
    Kamat, NR
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 187 - 190