A new compact dual-core architecture for AES encryption and decryption

This article presents a new compact architecture. consisting of two independent cores that process encryption and decryption simultaneously, for the Advanced Encryption Standard (AFS) algorithm. The corresponding new compact key generation unit with 32-bit datapath is also explored to provide round keys on the fly for encryption and decryption. A novel way to implement ShiftRows/InvShiftRows, one of the key designs in the compact 32-bit architecture, is proposed. The new AES implementation requires only 16 629 gate equivalents on the 0.35 mu m CMOS technology from CSMC Technologies Corporation, while providing encryption and decryption in parallel with 335 Mbits/s throughput.