Pre-sorted Forward-Backward NB-LDPC Check Node Architecture

被引：5

作者：

Harb, Hassan ^{[1
]}

Marchand, Cedric ^{[1
]}

Conde-Canencia, Laura ^{[1
]}

Boutillon, Emmanuel ^{[1
]}

Al Ghouwayel, Ali ^{[2
]}

机构：

[1] Univ Bretagne Sud, CNRS, Lab STICC, UMR 6285, Lorient, France

[2] LIU, CCE Dept, Beirut, Lebanon

来源：

2016 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS) | 2016年

关键词：

NB-LDPC; Check Node; Forward-backward; CODES;

D O I：

10.1109/SiPS.2016.33

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper deals with reduced-complexity NBLDPC check node implementation based on the Extended MinSum algorithm. We propose to apply a recently introduced presorting technique to the forward-backward architecture. The presorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees).

引用

页码：142 / 147

页数：6

共 27 条

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