Hardware Architecture for Advanced Image Processing

被引:0
|
作者
Grabowski, Kamil [1 ]
Napieralski, Andrzej [1 ]
机构
[1] Tech Univ Lodz, Dept Microelect & Comp Sci, PL-90924 Lodz, Poland
关键词
image analysis; multicore processing; biometrics; iris recognition; biomedical image processing; IRIS RECOGNITION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The computation speed offered by nowadays embedded systems allows combining advanced signal processing and data acquisition in dedicated architectures optimized for given applications. Such architectures can be used for 2D/3D signal analysis and reconstruction in such broad areas as: medical signal processing - tomography object reconstruction (USG, PET, CT, OCT, etc.), biomedical image analysis - automated object segmentation and diagnostic support, biometry - pattern recognition, etc. The technological advances in the scale of integration of integrated circuits as well as image acquisition and processing systems have played a major part in this trend. In particular, for medical image analysis common problems are content segmentation, analysis of selected objects, pattern estimation and storage. In the paper general architecture for advanced image processing is presented which can be adapted to specific needs, depending on intended use. This article describes a system for analysis of biometric data developed as part of the work conducted by the authors on the complete biometric identification system. Thus, the article focuses mostly on the biometrical iris identification system (1:N), chosen as an example well suited to the validation of the developed system. Several issues concerning efficient data processing using Field Programmable Arrays and Digital Signal Processors are presented on the basis of the described architecture. Algorithms computed on a desktop computer were adapted to this specialized, hardware-oriented architecture composed of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGA). Obtained results are presented and the developed system is compared with some commercially-available solutions for iris recognition.
引用
收藏
页码:3626 / 3633
页数:8
相关论文
共 50 条
  • [1] Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing
    Cuong Pham-Quoc
    Al-Ars, Zaid
    Bertels, Koen
    2013 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC), 2013, : 374 - 379
  • [2] AN EFFICIENT ARCHITECTURE FOR HARDWARE IMPLEMENTATIONS OF IMAGE PROCESSING ALGORITHMS
    Khalvati, Farzad
    Tizhoosh, Hamid R.
    2009 IEEE SYMPOSIUM ON COMPUTATIONAL INTELLIGENCE FOR IMAGE PROCESSING, 2009, : 20 - 26
  • [3] ADVANCED ARCHITECTURE FOR GRAPHICS AND IMAGE-PROCESSING
    ENGLAND, N
    PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1981, 301 : 54 - 57
  • [4] Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications
    Chandaka, Shravani
    Narayanam, Balaji
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2022, 38 (02): : 217 - 230
  • [5] Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications
    Shravani Chandaka
    Balaji Narayanam
    Journal of Electronic Testing, 2022, 38 : 217 - 230
  • [6] An Efficient Hardware Architecture for Block Based Image Processing Algorithms
    Kryjak, Tomasz
    Gorgon, Marek
    Komorkiewicz, Mateusz
    APPLIED RECONFIGURABLE COMPUTING, ARC 2016, 2016, : 54 - 65
  • [7] Architecture of an Integrated Software-Hardware System for Accelerated Image Processing
    Cyganek, Boguslaw
    COMPUTER VISION AND GRAPHICS, 2009, 5337 : 1 - 13
  • [8] An Efficient Hardware Architecture without Line Memories for Morphological Image Processing
    Clienti, Christophe
    Bilodeau, Michel
    Beucher, Serge
    ADVANCED CONCEPTS FOR INTELLIGENT VISION SYSTEMS, PROCEEDINGS, 2008, 5259 : 147 - 156
  • [9] Window memoization: an efficient hardware architecture for high-performance image processing
    Farzad Khalvati
    Mark D. Aagaard
    Journal of Real-Time Image Processing, 2010, 5 : 195 - 212
  • [10] Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors Networks
    George, Anuja
    Jayakumar, E. P. E.
    IEEE SENSORS JOURNAL, 2023, 23 (05) : 5382 - 5390