An Anti-Power Attacks Implementation of AES Algorithm in ASIC

被引：0
|
作者：
Yu, Siyang [1 ]
Li, Kenli [1 ]
Qin, Yunchuan [1 ]
Tang, Shaohua [2 ]
机构：
[1] Hunan Univ, Sch Informat Sci & Engn, Changsha 410082, Hunan, Peoples R China
[2] S China Univ Technol, Sch Comp Sci & Engn, Guangzhou 510641, Guangdong, Peoples R China
来源：
2013 IEEE 15TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2013 IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND UBIQUITOUS COMPUTING (HPCC_EUC) | 2013年
关键词：
AES; power analysis; mask; combination logic;
D O I：
10.1109/HPCC.and.EUC.2013.231
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we apply a protective strategy to the AES encryption algorithm. In order to reduce power consumption and correlation in the process of arithmetic operations, we change the trigger number and location in the hardware implementation by modifying the structure of the algorithm. Through the simulation platform, our Advanced Encryption Standard algorithm can effectively resist the Differential Power Analysis and Correlation power analysis. Compared with the mask and dynamic differential logic, the policy doesn't increase the complexity of the algorithm and the area.
引用
收藏
页码：1640 / 1646
页数：7
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