Low voltage stress-induced leakage current as a probe of interface defects and a monitor of the oxide reliability

Conduction behaviour of n-MOSFET capacitors with an oxide thickness (T-ox) of 18.5 angstrom was investigated before and after constant current stress. It was found that stress-induced leakage current (SILO) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analysed systematically, based on the assumption that the LV-SILC is due to interface trap-assisted tunnelling (ITAT) process. Using the LV-SILC as a probe, the generation of interface defects was probed by the LV-SILC. Interface defects in both anode and cathode are involved in the ITAT process, but the former dominates the oxide reliability. Based on the results of interface defect generation sensed by the LV-SILC, a new method to project lifetime (T-BD) or monitor the oxide reliability was set up.