Voltage Mode Multiple Valued Analog to Quaternary Mapping

Most of the digital processing is performed in the binary domain. With the increasing integration, chip area became an important resource to improve transistor density and energy efficiency. An alternative to reduce chip area is to increase the representation up to base B, domain D: (0, 1, 2, ... , B - 1) known as Multiple-Valued Logic (MVL) to decrease chip wirings due to the fact that approximately 70% chip area is devoted to the interconnections. For the digital processing of analog signals an Analog to Digital Mapping is needed. This proposal is a mapping and not a complete analog to digital converter (ADC) due to the fact that there are not any circuits to correct errors, for example: linearity, bits synchronization, etc. This work presents a voltage mode multiple valued analog to quaternary mapping architecture for two digits utilizing the chosen universal set of MVL operators presented in the literature for quaternary base B=4:eAND1, eAND2, eAND3, Successor, and Maximum that allows to design any MVL digital circuit. Simulations on Cadence Tools for the AMS CMOS 0,35 mu m technology will be presented to demonstrate concepts and circuit feasibility and functionality, showing correct behavior with respect to the specification and compatibility with the chosen universal set of gates.