InP-based HEMTs for high speed, low power circuit applications

被引：1
|
作者：
Adesida, I [1 ]
Mahajan, A [1 ]
Cueva, G [1 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
来源：
1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/ICSICT.1998.785953
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 mu m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance gmexp of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.
引用
收藏
页码：579 / 582
页数：4
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