A hardware approach to concurrent error detection capability enhancement in COTS processors

To enhance the error detection capability in COTS (commercial off-the-shelf)-based design of safety-critical systems, a now hardware-based control flow checking (CFC) technique will be presented. This technique, Control Flow Checking by Execution Tracing (CFCET), employs the internal execution tracing features available in COTS processors and an external watchdog processor (WDP) to monitor the addresses of taken branches in a program. This is done without any modification of application programs, therefore, the program overhead is zero. The external hardware overhead is about 3.5% using an Altera Flex 10K30 FPGA. For different workload programs, the execution time overhead and the error detection coverage of the technique vary between 33.3 and 140.8% and between 79.7 and 84.6% respectively. The errors are detected with about zero latency.