Robust built-in test of RF ICs using envelope detectors

被引:0
|
作者
Han, D [1 ]
Chatterjee, A [1 ]
机构
[1] Georgia Inst Technol, Atlanta, GA 30322 USA
关键词
D O I
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
To address growing production test costs, a low-cost built-in test solution for RF circuits is proposed that is robust to Process, Supply foliage and Temperature variations (PVT variations). The test solution consists of measuring the envelope of the output response to a two-tone test stimulus. This is a relatively low frequency signal compared to the nominal frequency of the RF device under test (DUT) and can therefore be sampled using an on-chip ADC The resulting test response waveform is analyzed using wavelet transforms. The corresponding wavelet coefficients are used to accurately predict the test specification values of the RF DUT in the presence of noise. The proposed test approach has been demonstrated for a 2.4GHz low noise amplifier designed in a 0.18um CMOS process and shows high prediction accuracy for the test specifications of the DUT in the presence of noise and PVT variations.
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页码:2 / 7
页数:6
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