Low noise single photon counting chip with energy window for hybrid pixel detector with precise offset and gain correction

We report on the design of an integrated circuit operating in a single photon counting mode for readout of hybrid pixel detectors. The prototype IC was designed and fabricated in CMOS 130 nm technology and consists of 23552 square shaped pixels of 75 mu m pitch. Each pixels consists of charge sensitive amplifier, shaper, two discriminators and two 14-bit counters. Additionally each pixel contains also novel key blocks for offset and gain trimming. The prototype IC works with two energy thresholds in the readout mode separate from exposure. In a continuous mode (with a zero dead time) the IC operates with single threshold. The readout pixel has an equivalent noise charge of 89 e- rms and dissipates only 25 mu W. Tests prove exceptional uniformity of IC: an offset spread below 12e- rms and a gain spread of only 3%.