Demonstration and analysis of accumulation-mode double-gate metal-oxide-semiconductor field-effect transistor

The property of an accumulation-mode double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) has thoroughly been investigated on the basis of experimental data and simulation results. Both accumulation- and inversion-mode DG-MOSFETs have been fabricated by novel vertical DG-MOSFET fabrication process technology. It is experimentally demonstrated that accumulation- mode DG-MOSFETs show a severe influence of channel thickness (T-Si) on threshold voltage (V-th) and subthreshold slope (S) as compared with inversion-mode ones. By decreasing T-Si, however, S is dramatically improved to the same value as that for the inversion-mode one. The short-channel effects (SCEs) for the accumulation-mode DG-MOSFETs have been explored using device simulation. The simulation result shows that, by decreasing T-Si to 10 nm, the trend of the SCEs for the accumulation-mode DG-MOSFETs becomes the same as that for the inversion-mode one down to an effective gate length of 10 nm. It is also demonstrated that, by using n(+)-DGs, an appropriate Vth as well as a low S can be attained for an accumulation-mode PMOS vertical DG-MOSFET.