A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s Single-channel Pipelined SAR ADC with a Current-mode Fine ADC in 28nm CMOS

被引：0

作者：

Moon, Kyoung-Jun ^{[1
,2
]}

Kang, Hyun-Wook ^{[1
]}

Jo, Dong-Shin ^{[1
]}

Kim, Mi-Young ^{[1
]}

Baek, Seung-Yeob ^{[2
]}

Choi, Michael ^{[2
]}

Ko, Hyung-Jong ^{[2
]}

Ryu, Seung-Tak ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Daejeon, South Korea

[2] Samsung Elect, Hwaseong, South Korea

来源：

2017 SYMPOSIUM ON VLSI CIRCUITS | 2017年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.

引用

页码：C94 / C95

页数：2

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