A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s Single-channel Pipelined SAR ADC with a Current-mode Fine ADC in 28nm CMOS

被引：0

作者：

Moon, Kyoung-Jun ^{[1
,2
]}

Kang, Hyun-Wook ^{[1
]}

Jo, Dong-Shin ^{[1
]}

Kim, Mi-Young ^{[1
]}

Baek, Seung-Yeob ^{[2
]}

Choi, Michael ^{[2
]}

Ko, Hyung-Jong ^{[2
]}

Ryu, Seung-Tak ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Daejeon, South Korea

[2] Samsung Elect, Hwaseong, South Korea

来源：

2017 SYMPOSIUM ON VLSI CIRCUITS | 2017年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.

引用

页码：C94 / C95

页数：2

共 23 条

[1] A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS
Moon, Kyoung-Jun
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (09) : 2532 - 2542
[2] A 9.78-ENOB 10 MS/s SAR ADC with a Common Mode Compensation Technique in a 28nm CMOS Node
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[3] A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS
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[4] A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers
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[5] A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling
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[6] A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch
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[7] An 8.38 fJ/conversion-step 0.6 V 8-b 4.35 MS/s asynchronous SAR ADC in 65 nm CMOS
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[8] An 8.38 fJ/conversion-step 0.6 V 8-b 4.35 MS/s asynchronous SAR ADC in 65 nm CMOS
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[9] A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS
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[10] A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic
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